NXP Semiconductors /MIMXRT1052 /IOMUXC_SNVS /SW_PAD_CTL_PAD_TEST_MODE

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Interpret as SW_PAD_CTL_PAD_TEST_MODE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SRE_0_Slow_Slew_Rate)SRE 0 (DSE_0_output_driver_disabled_)DSE0SPEED 0 (ODE_0_Open_Drain_Disabled)ODE 0 (PKE_0_Pull_Keeper_Disabled)PKE 0 (PUE_0_Keeper)PUE 0 (PUS_0_100K_Ohm_Pull_Down)PUS0 (HYS_0_Hysteresis_Disabled)HYS

DSE=DSE_0_output_driver_disabled_, ODE=ODE_0_Open_Drain_Disabled, PKE=PKE_0_Pull_Keeper_Disabled, HYS=HYS_0_Hysteresis_Disabled, PUS=PUS_0_100K_Ohm_Pull_Down, SRE=SRE_0_Slow_Slew_Rate, PUE=PUE_0_Keeper

Description

SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register

Fields

SRE

Slew Rate Field

0 (SRE_0_Slow_Slew_Rate): Slow Slew Rate

1 (SRE_1_Fast_Slew_Rate): Fast Slew Rate

DSE

Drive Strength Field

0 (DSE_0_output_driver_disabled_): output driver disabled;

1 (DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_): R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)

2 (DSE_2_R0_2): R0/2

3 (DSE_3_R0_3): R0/3

4 (DSE_4_R0_4): R0/4

5 (DSE_5_R0_5): R0/5

6 (DSE_6_R0_6): R0/6

7 (DSE_7_R0_7): R0/7

SPEED

Speed Field

2 (SPEED): medium(100MHz)

ODE

Open Drain Enable Field

0 (ODE_0_Open_Drain_Disabled): Open Drain Disabled

1 (ODE_1_Open_Drain_Enabled): Open Drain Enabled

PKE

Pull / Keep Enable Field

0 (PKE_0_Pull_Keeper_Disabled): Pull/Keeper Disabled

1 (PKE_1_Pull_Keeper_Enabled): Pull/Keeper Enabled

PUE

Pull / Keep Select Field

0 (PUE_0_Keeper): Keeper

1 (PUE_1_Pull): Pull

PUS

Pull Up / Down Config. Field

0 (PUS_0_100K_Ohm_Pull_Down): 100K Ohm Pull Down

1 (PUS_1_47K_Ohm_Pull_Up): 47K Ohm Pull Up

2 (PUS_2_100K_Ohm_Pull_Up): 100K Ohm Pull Up

3 (PUS_3_22K_Ohm_Pull_Up): 22K Ohm Pull Up

HYS

Hyst. Enable Field

0 (HYS_0_Hysteresis_Disabled): Hysteresis Disabled

1 (HYS_1_Hysteresis_Enabled): Hysteresis Enabled

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